1. Technical Field
The present invention relates generally to the data processing field and, more particularly, to a method, apparatus and system for controlling input/output adapter data flow operations in a data processing system.
2. Description of Related Art
In a data processing system, it is important to ensure that operations involving the flow of data to and from an input/output adapter (IOA) are kept ordered relative to one another in order to assure a consistent programming model between the IOA and the device driver software which is controlling the IOA. This is conventionally accomplished by following strict ordering rules with respect to the data flows. It is also important to keep operations involving the flow of data to and from one IOA separate from flows to and from other IOAs so as to eliminate performance bottlenecks due to interactions of the flows between different IOAs.
In a data processing system using PCI(Peripheral Component Interconnect)-Express, it is known that interactions between data flows can be controlled by providing the data processing system with a traffic class (TC) mechanism in conjunction with virtual channel (VC) resources provided by PCI-Express. VCs comprise a separate set of resources through which IOA data flow operations can be routed, and TCs provide a mechanism for defining a priority between data flow operations being routed through a VC. By using the TC mechanism in conjunction with VCs, IOA data flow operations, for example, DMA (Direct Memory Access) and MMIO (Memory Mapped Input/Output) operations, can be differentiated from one another to help eliminate bottlenecks and to generally improve overall system performance. In addition, the PCI-Express specifications describe a relaxed ordering (RO) bit in the transaction flow, which can be used to relax the ordering between operations within the same TC and VC.
The specifications for PCI-Express describe how different TCs/VCs and the RO bit are handled below a PCI Host Bridge (PHB), hut do not describe how TCs/VCs are associated with IOAs or how the RO bit is controlled for Load/Store operations. In general, there are not enough TCs/VCs to be able to provide every IOA unit with its own TC/VC. Accordingly, a mechanism is needed to associate a TC/VC with an IOA unit. In particular, such a mechanism is needed in order to associate Load/Store operations from the data processing system above the PHB to Direct Memory Access (DMA) operations from below the PHB because ordering rules between the two flows need to be obeyed when the two flows are combined, and are modified based on whether or not the flows are in the same TC/VC. In order to be able to separate flows for IOA units that are to be treated separately, for example, different IOAs or different functions of IOAs, a mechanism is needed to associate the Load/Store and DMA flows to/from an IOA unit. Similarly, a mechanism is needed to associate the RO bit state with a Load/Store operation to control the ordering between operations in the same TC/VC.
It would, accordingly, be advantageous to provide a mechanism for controlling input/output adapter data flow operations in a data processing system that includes a TC mechanism in conjunction with VC resources so as to be able to associate Load/Store and DMA flows to/from an input/output adapter. It would also, accordingly, be advantageous to provide a mechanism for controlling input/output adapter data flow operations in a data processing system that includes an RO bit in the transaction, so as to be able to relax the ordering between operations to/from an IOA.